Tim Michels, CTO

Rich Lee, Tim Michels, and Danny ONeillTim Michels is co-founder, Chief Technology Officer and Principal Architect of AtSpex's FAST PINS. With 19 years of design experience, Tim has led the successful development of many ASIC and FPGA devices as well as IP cores. He has also been a key contributor in the successful architecture, design, and implementation of a multitude of complex products including ATE test systems, LAN switches, WAN routers, Server Load Balancing systems, and 802.11 wireless Access Points. Tim is well versed in all the major networking standards, protocols, QoS strategies, and queuing systems.

Prior to founding AtSpex, Tim developed FPGA based 802.11 multi-MAC and baseband components for Vivato Networks wireless access points. At Allegro Networks, Tim conducted independent architectural reviews of the multi-router system and was ASIC lead for an OC-48 Network Interface FPGA. With F5 Networks, Tim created the ASIC group (staff & tooling), developed the architecture for the companies first load balancing ASIC, and helped create a new system architecture utilizing a mix of merchant and custom silicon.

As system architect and ASIC lead, Tim helped create the PowerRail Gigabit Ethernet switch family for Packet Engines/Alcatel. During this time, Tim also led a design team in the development of a network processor. Earlier at Packet Engines, Tim was a key developer of the companies' suite of Ethernet IP cores. Tim also served as Lead Design Engineer for Logue McDonald Automation, an ATE systems company where he was a primary architect of the LMA 750, a 100/200 MHz bipolar, per-pin VLSI Test System.

Tim's unique blend of ASIC networking design and ATE IC Tester architecture expertise culminated in our AtSpex Broadband-to-the-Testhead(tm) implementation: 100M deep pattern loads via Ethernet DMA PCI Controller using the IP stack provided in an embedded Linux SBC. Tim led the development of our PEG- Pin Electronics Gate Array. Each PEG incorporates our PCI controller, a sustained 267 MHz 533MB/s 1GB DDR2 DIMM VMM Vector Memory Controller and our VLSI Test Controller for 100/200/400MHz Vector Rate Modes supplying the waveformatters, error capture and pin electronics for 192 DUT-facing pins. Each of the 4 PEG's is implemented in 1000+ pin packages and times successfully @200MHz.

Tim has a BSEE degree from Gonzaga University and has been awarded four US patents in data networking as a result of his work at Packet Engines. Tim has proven leadership and communication skills and has led design teams in the successful development of highly complex devices and products.

Rich Lee, System Design Mgr Principal Engineer

BSEE University of Wyoming, MSEE Washington State University Mr Lee is a co-founder and system level architect

Danny ONeill, General Manager, WW Sales and Applications Mgr

Rich Lee and Danny ONeillBSEE University of Massachusetts. Danny ONeill is co-founder, and World Wide Sales and Applications Mgr of At-Spex Test Systems. Mr ONeill was Gen Rad's Western US Area Sr Account Mgr, Product Specialist and FAE for the GR1731 Analog/Linear, GR1732 Digital, 1734 Memory Testers and GR125 VLSI Test System from 1980-90. He was Logue McDonald's National Sales Manger from 1990-95 with direct sales of $8M, cofounded LMO Test Systems in 96 and served as their WW Sales Mgr from 1996-2004.

With respect to At-Spex's FAST PINS, Mr ONeill has authored "Memory Test via MARCH Algorithmic Test Pattern Development using Verilog Test Bench Simulation for DDR2/DDR3 Components and DIMMs to Auto-generate JEDEC VLSI Test Vectors", " Automating FPGA/CPLD Test Program Development for VLSI Test Systems via Verilog Test Bench" and co-authored with Jim Perry "PCI Ethernet MAC PHY Mixed Signal Loopback Testing".

Danny's most recent papers:

Statement of Work and Test Plan for Altera Stratix HC1S60F1020AG

MARCH Algorithmic Test Pattern Development for DDR2/DDR3 Components and DIMMs

IC FPGA Design to Test Plan and Industrial Temperature Test Procedure

1020 pin SoC Step-By-Step Test Development and Debug

Complex VLSI Test Vector Development PCI 10/100 Ethernet MAC Controller With Integrated PHY