Test Plan Development
Altera Stratix HC1S60F1020AG

Statement of Work and Test Plan
for Altera Stratix HC1S60F1020AG

Authors: James Perry and Danny ONeill

Purpose

This document details the plan to develop a dual-use custom board to test an Altera Hardcopy Stratix PN HC1S60F1020AG. The custom DUT card enables multiple test reads of the ID register on the device over the RACEway++ interface of this part at cold temperature with an LMO500 tester.

The custom board will also be designed to support accesses to the UUT without the LMO500 tester connected by supplying the mechanical and electrical interconnect via the RACEway++ interface to the HC1S60F1020AG for an alternate controller. Power and control signals must be supplied by external means when operating in this mode.

Deliverables

No. Item Description
1 LMO500 test project and program Includes Test Source, Test Patterns, PIN DEFs, and pin2channel files
2 Dual Use Custom DUT Card Includes schematic, test socket for a 1020 pin FBGA (Fineline Ball-Grid Array: 32x32 array minus the corner pins, 1mm pitch), and receptacle
3 DUT Card Artwork (B/W) DUT card black and white artwork

Click image to enlarge

4 DUT Card Artwork (color) DUT card artwork color image

Click image to enlarge

References

Ref Item Title
1 HardCopy Stratix Device Family Datasheet
2 RACEway Interlink - Data Link and Physical Layers, Rev. 1.6.3, September, 1998
3 Altera 1020 Pin Fineline Ball-Grid Array (FBGA), Option 1-Flip Chip (pg 259 of Package Information Datasheet for Altera Devices)
4 Ironwood Electronics Socket Adapter
5 LMO500 Series TCOMM User's Manual
6 LMO500 Series LMOTC User's Guide
7 LMO500 Series VCD User's Guide

Assumptions

  1. UUT initializes at power up. Tester does not write any registers.
  2. LMO500 Tester uses RACEway++ Interlink to read ID register of UUT.
  3. Dual use, custom DUT card also supplies mechanical and electrical interface for separate accesses to UUT via RACEway++ Interlink with separate power supplies and control signals supplied by customer.

Overview

Table 1 shows the UUT pins. The LMO500 does the following:

Table 1 UUT Pin Description
UUT Pin Name Type Description
RACEway++ Interface
V1 REQ1    
V4 REQ0    
W1 RPLYIO    
V3 STROBEIO    
W2 RDCONIO    
W3
W4
Y1
Y2
Y3
Y4
AA2
AA3
AB2
AB3
AA5
AA4
AB1
AC2
AD1
AD2
AD4
AD3
AC4
AC3
AE1
AE2
AE3
AE4
AF1
AF2
AF3
AF4
AC2
AC1
AC3
AC4
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
IO RACEway++ data pins carry Route, Address, and Data between master and slave

Custom DUT board control signals to UUT RACEway++ interlink module, block diagram

Figure 1. Custom DUT Board Control Signals to UUT RACEway++ Interlink Module, showing a block diagram of the RACEway++ module to be tested.

High Level Test Description

The high level functional test flow for the Altera Stratix HC1S60F1020AG is:

  1. LMO500 tester applies power to the UUT and reads UUT ID register at speed.
  2. DUT card with UUT installed can also be separately powered and accessed via RACEway++ Interlink for ad hoc accesses by customer.

Figure 2 Custom DUT Card Conceptual Block Diagram (click to open a PDF)

Figure 3 HC1S60F1020AG DUT Card Schematic

The Tester FPGA J11 and the DUT are a direct short thru J3. The LMO J2 is not connected, and therefore not a stub. When the jumper connector is shorted across the LMO J2 and the DUT J3, the Tester FPGA J11 is disconnected: so in no situation are Tester FPGA J11, DUT J3, and LMO J2 connected. J4 is the external Raceway connector.

Appendix A RACEway++ Read Access Timing

Error! Reference source not found. shows HC1S60F1020AG read access timing.

HC1S60F1020AG read access timing

Figure 4.

Appendix B How to read LMO500 Test Vectors

Test Program Overview

A test program for the LMO500 contains the following files:

The .ts file contains tests to do various parametric measurements on the UUT while it executes vectors in the .cvf file.

The .p2c and .def files define the device pins and map them to the tester channels while considering the DUT card pin mappings.

The .cvf file is one of several files that make up a test program for the LMO500. The .cvf file defines the functional operation of the UUT.

CVF File

The .cvf file contains a header section for pin data and a test vector section. These sections are separated by a VFormat statement which defines the format of the vector lines that follow it.

The test vector section exercises the UUT functionality. It contains test vectors and microinstructions. The test program executes the test vectors sequentially unless a microinstruction calls for a loop, jump, or halt to execution.

Loadset statements in the vector section of the test program allow pull-ups and pulldowns to be applied various pin groups in the test program.

The vector data section of the .cvf file contains:

Each column in the .cvf file is mapped to a pin on the tester and to the UUT by a pin definition file. The pin definition file defines whether each pin is an:

The vector data contains test vectors. Each vector defines what the tester is to drive or read on each pin. A test vector can also have a microinstruction appended that allows conditional and repeat loop control for various test vectors.

For tester outputs, the tester vector contains:

The test vector contains expected values for what the tester should read when that particular vector executes:

""

Figure 5.

Figure 6. The image above is the original Allegro PWB pinout highlighting the Raceway++ signals and the DUT power and ground pins. In order to map it to the Bottom View below this image needs to be rotated 90 degrees counter clockwise and then flipped on its vertical axis.

Figure 7.

Figure 8. New bottom view

Figure 9. RaceWay Timing Waveforms and Master/Slave Signaling Description

  1. A master shall initiate a transaction by asserting REQO coincident with φ0 while driving the ROUTE word onto DATA[31:0] (see Figure 13) p.44
  2. REQO is received at the REQI pin coincident with φ1 on the slave side of the interface (see Figure 14).
  3. The slave side of the interface shall drive REPLYIO low (from its inactive high-impedance state) coincident with φ0 one clock edge after sampling REQI active.
  4. The slave side shall assert CHANGE TO ADDRESS coincident with φ1 on the REPLYIO line when it is ready to receive the ADDRESS (see Figure 15)
  5. The master side of the interface shall drive the ADDRESS word onto DATA[31:0] coincident with either two or four cycles after receiving CHANGE TO ADDRESS
  6. The slave side of the interface may sample a valid ADDRESS beginning with the fourth clock edge after asserting CHANGE TO ADDRESS, up to the same cycle DSTROBE is received (see Section 5.9.5).
  7. The master side shall stop driving the ADDRESS one cycle after asserting the first DSTROBE
  8. The slave shall assert DSEN on the REPLYIO line coincident with φ0 when it is able to receive a data word (8 bytes) during a write, or when it has a data word available during a Read (see Figure 16). The master shall receive DSENs coincident with φ1.

Figure 11. Configuration Vector Format

Figure 12. PIN DEF

Figure 13. Stratix Hardcopy Questions

Figure 14. Stratix EP 1S60 F1020 Device Package Diagram

Figure 15. Tester FPGA Pinout

Filter Circuit

Node 0 P5CE Banks 1,2,3 7  Sheet 4 of 26 cc-p2n512j-t_r0.pdf

ND0_AACKN

4.7k pup to 2.5V

AM22

ND0_ARTRYN

4.7k pup to 2.5V

AJ21

ND0_BGN

4.7k pup to 2.5V

AE20

ND0_INTN

4.7k pup to 2.5V

AK30

ND0_SMINTN

4.7k pup to 2.5V

AG24

ND0_TAN

4.7k pup to 2.5V

AH20

ND0_TEAN

4.7k pup to 2.5V

AJ20

ND0_TBSTN

4.7k pup to 2.5V

AM24

ND0_TSN

4.7k pup to 2.5V

AL22

ND0_GBLN

4.7k pup to 2.5V

AJ28

 

 

 

ND0_BRN

470 Ohm pup to 2.5V

AK21

ND_PLL_ENA

33 Ohm pup to 2.5 / depop 33 Ohm pdown to gnd

AF19

ND_PORSEL

depop 33 Ohm pup to 2.5 / 33 Ohm pdown to gnd

AG15

ND_DRV_SRTH

depop 33 Ohm pup to 2.5 / 33 Ohm pdown to gnd

AC31

MREF_SSTL0

filter circuit

E21,E23,E25,E27