IC Test Engineering Tutorial

Applications Note
Complex VLSI Test Vector Development
PCI 10/100 Ethernet MAC Controller With Integrated PHY

Register Level Test Plan

This assumes writes to configuration registers (CRn) have been completed.

Write 0x00000001 to CSR0 (offset PBAR1 + 0x00) <----------p 17/66 via the PCI Access Register, Reset all internal HW excluding the transceivers and config registers
Write 0x8000 to XR0 (offset PBAR1 + 0xB4) <--------p 31/66 via the Transceiver Control Register, Reset the transceiver
Write 0xF0000000 to CSR3 (PBAR1 + 0x18) <--------p 17/66 Rec'v Descriptor Base Address(RX_PTR = 0x80000000)
Write 0xFF000000 to CSR4 (PBAR1 + 0x20) <--------p 17/66 Transmit Descriptor Base Address(TX_PTR = 0x40000000)
Write 0x3000 to XR0 (PBAR1 + 0xB4) <---------------- p 31/66 Autonegotiation enabled and 100Mbs selected
Wait 6 seconds <--------This is for the PHY to autonegotiate a link to itself.
Write 0x0100 to XR0 (PBAR1 + 0xB4) <---------------- p 31/66 Disable Autonegotiation by driving Bit [12]=0 so that Full Duplex can be selected by driving Bit[8]=1
//Write 0x0020204A to CSR6 (PBAR1 + 0x30) <---------------Currently writing 0x002820C2 which means we're disabling SQE, enabling multicast, and not passing bad packet. Change it to pass bad packet.
Write 0x000820CA/0x000824CA to CSR6 (PBAR1 + 0x30) <-------- p19/66 in the Network Access Register set the Stop Transfer Bit [13]= 1 to start

Transmit Descriptor Read - (Reads the following 4 D-Words From 0x40000000.)

The ST will now read the following: 4 DWORDS from 0xFF000000. The tester must respond with this data:

0x80000000 <-----------------------TX DES0
0x62000040 <-----------------------TX DES1 first packet and end of ring. Buffer 2 byte count= 2**6= 64 bytes- 4 bytes per D-Word or 16 D-Word burst
0x20000000 <------------ TX Buffer Start Address programmed to A0000000
0x00000000 <----------------------TX DES3 s/b don't care, but zero it out.

Receive Descriptor Read -(Reads the following 4 D-Words from 0x80000000.) The ST will now read the following DWORDs from 0xF0000000. The tester must respond with this data:

0x80000000 <-----------------RXDES0 set Own Bit [31]
0x02000080 <------------------
0x10000000 <----------RX Buffer Start Address programmed to C0000000
0x00000000 <----------------------RX DES3 (s/b don't care, but zero it out)

TX Buffer Read - (Issues A0000000.) The ST will now read the following 16 words from the tester:

0x00000000
0x55555555
0xAAAAAAAA
0xFFFFFFFF
0x0F0F0F0F
0x5A5A5A5A
0x00FF00FF
0xAA55AA55
0x00000000
0x55555555
0xAAAAAAAA
0xFFFFFFFF
0x0F0F0F0F
0x5A5A5A5A
0x00FF00FF
0xAA55AA55

2nd Transmit Descriptor Read -(Issues C0000000 give the STE, nGNT, nTRDY, nDEVSEL.) The ST will now read the following 4 DWORDS from 0xFF000000. The tester must respond with this data:

0x80000000
0x62000040
0x20000000
0x00000000

RX Buffer Write - The ST will now write the following:

18 words to the tester: <--------------------------- It should be able to burst as long as REQ and GNT are asserted. P. 15 of CVF, Give STE nGNT, nTRDY, nDEVSEL
0x00000000
0x55555555
0xAAAAAAAA
0xFFFFFFFF
0x0F0F0F0F
0x5A5A5A5A
0x00FF00FF
0xAA55AA55
0x00000000
0x55555555
0xAAAAAAAA
0xFFFFFFFF
0x0F0F0F0F
0x5A5A5A5A
0x00FF00FF
0xAA55AA55
0x1B43BCF0
0x00440028

PCI Configuration Read

  1. All PCI signals are in their unasserted state (3.3V level) except IDSEL, which is 0.
  2. The host (tester) simultaneously changes CBE[3:0] to 1010, drives AD[31:0] to all 0s, drives FRAME to 0, and drives IDSEL to 1.
  3. The host waits for the next rising edge of the PCI clock.
  4. After the rising edge, the host then changes IRDY to 0, FRAME to 1, CBE to 0000, stops driving AD[31:0], and drives IDSEL to 0.
  5. The ST part should now drive DEVSEL low.
  6. Within a few clock cycles the ST part should drive TRDY low, and drive AD[31:0] to 0x0981104A.

logic analyzer capture from an actual ST10/100 part.

Figure 1. Logic analyzer capture from an actual ST10/100 part. This assumes that the clock is running, reset is unasserted, and the device is out of reset.

Table 1. The necessary state of the CBE[3:0]
  Read Write
CRn  1010 1011
CSRn 0110 0111

PCI Configuration Write to CR5 w/ Base Address as it is the bottom line to accessing CSR's

Figure 2. PCI Configuration Write to CR5 w/ Base Address as it is the bottom line to accessing CSR's

 

CSR0 Write

Figure 3. CSR0 Write

 

Figure 4.

Logic Analyzer Capture of the System Level DUT Signaling

Here is a capture of the ST part reading a transmit descriptor. The ST parts initiates a cycle to host memory. The address is set in CSR4 and in this case is 0x0198F040. The ST part does a burst read, which means it reads more than one DWORD. This is indicated by the four consecutive DATA cycles in that attached capture. A burst is indicated by the master holding FRAME# and IRDY# low after the initial address phase. The following capture shows all four DWORDS in the transmit descriptor being read.

Logic Analyzer Capture of the System Level DUT Signaling

Figure 5. DUT Reading the Transmit Descriptor

 

            

Table 1. System Level DUT Logic Analyzer Capture

Sample#CommentCYCLEAdd[32]Data[32]AD[31-0]C/BE[3-0]FRAME#IRDY#DEVSEL#TRDY#STOP#Time_Rel
-3 IDLE  0183C7540110111110. ns
-2 IDLE  0183C75401101111130. ns
-1write 0x00000001 to CSR0MEM WRFF1FFC00 FF1FFC000111011113.57797 s
0 DATA 000000010000000100001000160. ns
1 IDLE  0000000100001111130. ns
2write 0x8000 to XR0MEM WRFF1FFCB4 FF1FFCB401110111124.45 us
3 DATA ----8000819F800011001000160. ns
4 IDLE  819F800011001111130. ns
5write rcv desc address to CSR3MEM WRFF1FFC18 FF1FFC1801110111121.78 us
6 DATA 0162A8E80162A8E800001000160. ns
7 IDLE  0162A8E800001111130. ns
8write xmt desc address to CSR4MEM WRFF1FFC20 FF1FFC2001110111120.82 us
9 DATA 016931A8016931A800001000160. ns
10 IDLE  016931A800001111130. ns
11write 0x3000 to XR0MEM WRFF1FFCB4 FF1FFCB401110111120.16 us
12 DATA ----3000819F300011001000160. ns
13 IDLE  819F300011001111130. ns
14read XR1, verify bit 2 is setMEM RDFF1FFCB8 FF1FFCB801100111172.54 us
15 DATA ----78090000780911001000160. ns
16 IDLE  0000780911001111130. ns
85write 0x0020244A to CSR6MEM WRFF1FFC30 FF1FFC30011101111116.885 ms
86 DATA 0020244A0020244A00001000160. ns
87 IDLE  0020244A00001111130. ns
88ST reads xmit descriptorMEM RD016931A8 016931A8011001111210. ns
89 DATA 8000000080000000000000001870. ns
90 DATA 620000406200004000000000130. ns
91 DATA 017B99A8017B99A800000000130. ns
92 DATA 000000000000000000001000130. ns
93 IDLE  0000000000001111130. ns
98ST reads rcv descriptorMEM RD0162A8E8 0162A8E8011001111210. ns
99 DATA 800000008000000000000000160. ns
100 DATA 020000800200008000000000130. ns
101 DATA 016943800169438000000000130. ns
102 DATA 000000000000000000001000130. ns
103 IDLE  0000000000001111130. ns
104ST reads xmt bufferMEM RD017B99A8 017B99A8011001111210. ns
107 DATA 0000000000000000000000001420. ns
108 DATA 555555555555555500000000130. ns
109 DATA AAAAAAAAAAAAAAAA00000000130. ns
110 DATA FFFFFFFFFFFFFFFF00000000130. ns
111 DATA 0F0F0F0F0F0F0F0F00000000130. ns
112 DIS+DATA 5A5A5A5A5A5A5A5A00000000030. ns
113 IDLE  0000000000001111160. ns
114 MEM RD017B99C0 017B99C001100111190. ns
115 DATA 00FF00FF00FF00FF000000001600. ns
116 DATA AA55AA55AA55AA5500000000130. ns
117 DATA 000000000000000000000000130. ns
118 DATA 555555555555555500000000130. ns
119 DATA AAAAAAAAAAAAAAAA00000000130. ns
120 DATA FFFFFFFFFFFFFFFF00000000130. ns
121 DATA 0F0F0F0F0F0F0F0F00000000130. ns
122 DATA 5A5A5A5A5A5A5A5A00000000130. ns
123 DATA 00FF00FF00FF00FF00000000130. ns
124 DATA AA55AA55AA55AA5500001000130. ns
125 IDLE  AA55AA5500001111130. ns
128ST reads xmit descMEM RD016931A8 016931A801100111190. ns
129 DATA 8000000080000000000000001540. ns
130 DATA 620000406200004000000000130. ns
131 DATA 017B99A8017B99A800000000130. ns
132 DATA 000000000000000000001000130. ns
133 IDLE  0000000000001111130. ns
134ST reads xmit bufferMEM RD017B99A8 017B99A8011001111120. ns
141 DATA 000000000000000000000000160. ns
142 DATA 555555555555555500000000130. ns
143 DATA AAAAAAAAAAAAAAAA00000000130. ns
144 DATA FFFFFFFFFFFFFFFF00000000130. ns
145 DATA 0F0F0F0F0F0F0F0F00000000130. ns
146 DIS+DATA 5A5A5A5A5A5A5A5A00000000030. ns
147 IDLE  0000000000001111160. ns
148 MEM RD017B99C0 017B99C0011001111210. ns
149 DATA 00FF00FF00FF00FF000000001510. ns
150 DATA AA55AA55AA55AA5500000000130. ns
151 DATA 000000000000000000000000130. ns
152 DATA 555555555555555500000000130. ns
153 DATA AAAAAAAAAAAAAAAA00000000130. ns
154 DATA FFFFFFFFFFFFFFFF00000000130. ns
155 DATA 0F0F0F0F0F0F0F0F00000000130. ns
156 DATA 5A5A5A5A5A5A5A5A00000000130. ns
157 DATA 00FF00FF00FF00FF00000000130. ns
158 DATA AA55AA55AA55AA5500001000130. ns
159 IDLE  AA55AA5500001111130. ns
160ST writes to rcv bufferMEM WR01694380 0169438001110111156.43 us
161 DATA 000000000000000000000000160. ns
162 DATA 555555555555555500000000130. ns
163 DATA AAAAAAAAAAAAAAAA00000000130. ns
164 DATA FFFFFFFFFFFFFFFF00000000130. ns
165 DATA 0F0F0F0F0F0F0F0F00000000130. ns
166 DATA 5A5A5A5A5A5A5A5A00000000130. ns
167 DATA 00FF00FF00FF00FF00000000130. ns
168 DATA AA55AA55AA55AA5500000000130. ns
169 DATA 000000000000000000000000130. ns
170 DATA 555555555555555500000000130. ns
171 DATA AAAAAAAAAAAAAAAA00000000130. ns
172 DATA FFFFFFFFFFFFFFFF00000000130. ns
173 DATA 0F0F0F0F0F0F0F0F00000000130. ns
174 DATA 5A5A5A5A5A5A5A5A00000000130. ns
175 DATA 00FF00FF00FF00FF00000000130. ns
176 DATA AA55AA55AA55AA5500001000130. ns
177 IDLE  AA55AA5500001111130. ns
178 MEM WR016943C0 016943C00111011114.44 us
179 DATA 1B43BCF01B43BCF000000000160. ns
180 DATA 004410280044102800001000130. ns
181 IDLE  0044102800001111130. ns
182ST writes to rcv descMEM WR0162A8E8 0162A8E8011101111150. ns
183 DATA 004413200044132000001000160. ns
184 IDLE  0044132000001111130. ns
185ST reads rcv descMEM RD0162A8E8 0162A8E8011001111120. ns
188 DATA 00441320004413200000000011.02 us
189 DATA 020000800200008000000000130. ns
190 DATA 016943800169438000000000130. ns
191 DATA 000000000000000000001000130. ns
192 IDLE  0000000000001111130. ns
193ST writes to xmt descMEM WR016931A8 016931A8011101111210. ns
194 DATA 2A0B00802A0B008000001000160. ns
195 IDLE  2A0B008000001111130. ns
196ST reads xmt descMEM RD016931A8 016931A8011001111210. ns
199 DATA 2A0B00802A0B0080000000001780. ns
200 DATA 620000406200004000000000130. ns
201 DATA 017B99A8017B99A800000000130. ns
202 DATA 000000000000000000001000130. ns
203 IDLE  0000000000001111130. ns

TX Descriptor Read

Test Vector Micro-instructions, UUT Synchronization

Figure 6. Test Vector Micro-Instructions, UUT Synchronization - the test vector code to do a TX Descriptor Read

  1. Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:)
  2. The tester, which is now the Target, then gives the STE its GNTn
  3. Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is that the STE issues the transmit descriptor base address 0x40000000 on the PCI AD bus, and the Memory Read command (0x6) on the command bus, and asserts FRAME#
  4. Burst read, which means it reads more than one DWORD. This is indicated by the four consecutive DATA cycles in Figure 1. A burst is indicated by the master Holding FRAME# and IRDY low after the initial address pulse. Figure 1 shows all folder DWORD in the Transmit Descriptor being read
  5. Insert dummy turn-around per the Read Transaction waveform
  6. The Target then gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0; the STE begins reading the TX Descriptor first of 4 DWORDS TDES0 (pointed to by the transmit descriptor address) on the next PCI Klunk. (Reading means the tester has to drive the TXDES0 own bit MSB 31 Hi.) TRDYn is used to hold off the master until the target is ready. On the next the PCI Clock, the tester provides TXDES1 = 0x62000040, which sets the buffer size. 40= 0100 0000 sets the 2 byte count to 2**6= 64 bytes. 64 bytes/4 bytes per DWORD= Burst Length of 16. On the next PCI Clock TXDES2, which is the TX Buffer Address 0xA0000000, is written into (read by) the STE.

RX Descriptor Read

RX Descriptor Read

Figure 7. Test Vector Micro-Instructions, UUT Syncronization - the test vector code to do a RX Descriptor Read

  1. Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:)
  2. The tester which is now the Target, then gives the STE its GNTn
  3. Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is that the STE issues the receive descriptor base address 0x88000000 on the PCI AD bus, and the Memory Read command (0x6) on the command bus, and asserts FRAME#
  4. Insert dummy turn-around per the Read Transaction waveform
  5. The Target then gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0; the STE will then begin reading the RX Descriptor first of 4 DWORDS RDES0 (pointed to by the transmit descriptor address) on the next PCI Klunk. Note: reading means the tester has to drive the RXDES0 own bit MSB 31 Hi. TRDYn is used to hold off the master until the target is ready. On the next the PCI Clock, the tester provides TXDES1 = 0x62000040 which sets the buffer size. 40= 0100 0000 sets the 2 byte count to 2**6= 64 bytes. 64 bytes/4 bytes per DWORD= Burst Length of 16. The next PCI Clock RXDES2, which is the RX Buffer Address 0xC0000000, is written into (read by) the STE

TX Buffer Read

TX Buffer Read

Figure 8. TX Buffer Read

  1. Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:)
  2. The tester, which is now the Target, then gives the STE its GNTn
  3. Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is that the STE issues the Transmit Buffer Start Address 0xA0000000 on the PCI AD bus, and the Memory Read command (0x6) on the command bus, and asserts FRAME#
  4. The Target then gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0; the STE asserts IRDY# active Low out then begins reading the TX Buffer
  5. The DUT will now read the following 16 words from the tester

RX Buffer Write

RX Buffer Write

Figure 9. RX Buffer Write

  1. Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:)
  2. The tester, which is now the Target, then gives the STE its GNTn
  3. Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is that the STE issues the Receive Buffer Start Address 0xC0000000 on the PCI AD bus, and the Memory Write command (0x7) on the command bus, and asserts FRAME#
  4. The DUT will now write the following 18 words to the tester. The Target then gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0, the STE will then begin reading the RX Buffer

 

How PCI Works

How PCI works diagram

Figures 10 and 11. The CPU provides the STE 10/100 with action commands and pointers to the data buffers that reside in host main memory. The STE 10/100 independently manages these structures and initiates burst memory cycles to transfer data to and from them. The STE 10/100 uses the Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line) command for burst accesses to control structures. For all write accesses to the control structure the STE 10/100 uses the Memory Write or Memory Write and Invalidate (MWI) commands.

How PCI Works

Figure 12. A basic read transaction starting with an address phase which occurs when FRAME# is asserted for the first time and occurs on clock 2. During the address phase AD[31:0] contains a valid address and C/BE[3:0] contains a valid bus command.

  1. Address Phase
  2. 1a) Initiator identifies the target via the ADX and the type of transaction via the command bus
    1b) Initiator also asserts FRAME# to indicate the presence of valid ADX and command

  3. Data Phase
  4. 2a) When the Target determines it is the selected target, it must claim the transaction by asserting DEVSEL#. If the Initiator doesn't sample DEVSEL# asserted, it aborts the transaction
    2b) The Initiator indicates the last data transfer of a burst in progress by deasserting FRAME# and asserting IRDY#. When the last data transfer has been completed, the Initiator returns the PCI Bus to idle by deasserting it's ready line IRDY#, so that another master can detect that the bus is idle by detecting FRAME# and IRDY# both deasserted on the same rising edge of the PCI Clock
    2c) When the Target samples IRDY# asserted and FRAME# deasserted in a data phase, it realizes this is the final data phase. However the data phase will not complete until the target has also deasserted TRDY#

  5. Config Page 121 of PCI System Architecture Fourth Edition by Tom Shanly and Don Anderson
  6. 3a) To access Configuartion Registers, a config command must be initiated, and the device must sense it's IDSEL input asserted during the Address Phase
    3b) AD[10:8] selects the function; AD[7:2] during the ADX Phase select one of the Target function's 64 DWORDS of Config Space

STE 10/100A Datasheet

Beginners Guide to Ethernet 802.3

Reading the Control and Status Register CSR5

(from the STE10/100A datasheet pages 19-20)

Reading the Control and Status Register

 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F C 3 6 5 4 1 0
1 1 1 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0
  1. Read the following from CSR5 [31:0] (Control and Status Register)
  2. 'HHHHHH' from CSR5 [31:26] Reserved.
  3. 'LLL' from CSR5 [25:23] BET bits. This field is valid iff FBE bit 13 Fatal Bus Error is set. But FBE = 0 therefore No Fatal Bus Error.
  4. 'LHH' from CSR5 [22:20] Transmit State FIFO Fill. Read the data from memory and put into FIFO
  5. 'LHH' from CSR5 [19:17] Receive State wait for receiving data.
  6. 'L' from CSR5 [16] Normal Interrupt Status Summary. Default State 0
  7. 'L' from CSR5 [15] Abnormal Interrupt Status Summary. Default State 0
  8. 'H' from CSR5 [14] Reserved.
  9. 'L' from CSR5 [13] Fatal Bus Error. Default State 0
  10. 'H' from CSR5 [12] Reserved.
  11. 'L' from CSR5 [11] General Purpose Timer Timeout. Default State 0
  12. 'H' from CSR5 [10] Reserved
  13. 'L' from CSR5 [9] Receive Watchdog Timeout. Default State 0
  14. 'L' from CSR5 [8] Receive Process Stopped. Default State 0
  15. 'L' from CSR5 [7] Receive Descriptor Unavailable. Default State 0
  16. 'L' from CSR5 [6] Receive Completed Interrupt. Default State 0
  17. 'L' from CSR5 [5] Transmit Under-Flow. Default State 0
  18. 'H' from CSR5 [4] Reserved
  19. 'L' from CSR5 [3] Transmit Jabber Timer Time-out. Default State 0
  20. 'L' from CSR5 [2] Transmit Descriptor Unavailable. Default State 0
  21. 'L' from CSR5 [1] Transmit Process Stopped. Default State 0
  22. 'L' from CSR5 [0] Transmit Completed Interrupt. Default State 0
  23. Set all other values to defaults.

Table 2. CSR5(offset = 28h), SR - Status Register

Reading the Control and Status Register CSR5
Reading the Control and Status Register CSR5

Writing the Network Access Register CSR6

Write 0x000824CA To CSR6 (PBAR1 + 0x30)

  1. Write the following to CSR6 [31:0] (Network Access Register) "00000000001010000010000011000010":
  2. '1' to CSR6 [21] Store and Forward (SF) so UUT ignores transmit threshold setting.
  3. '1' to CSR6 [13] Stop Transmit (ST) to start Transmit.
  4. '1' to CSR6 [6] Promiscuous mode (PR) so UUT accepts any good packet.
  5. '1' to CSR6 [1] Start/Stop Receive (SR) to set Receive processor to run.
  6. Set all other values to defaults.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 2 8 2 4 C A
0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0

CSR6 [21] SF Store and Forward for transmit enable.
CSR6 [19] SQE set to 1 disables SQE function.
CSR6 [13] ST Stop Transmit set to start.
CSR6 [10] OM Operating Mode bit set to enable MAC Loopback
CSR6 [7] MM Multicast Mode set to receive all multicast packets.
CSR6 [6] PR Promiscuous Mode set to receive any good packet.
CSR6 [3] PB Pass Back packet set to receive any packets passing address filter, including runt packets, CRC error, truncated packets. For receiving all bad.
CSR6 [1] SR Start Stop Receive processor will enter running state.

Tulip Software Driver CSR6 Register Programming.

Table 3. CSR6(offset = 30h), NAR - Network Access Register

Network Access Register

Scope Capture of Test Pattern Execution

Table 3
Picture # Trace Description Trace
1. Shows CBEB0 indicative of a 16 word write, followed by a read of CSR5 and then STE writes two more FCS words to RX buffer. Trace 1: FRAME# Trace 2: TRDY# Trace 3: PCI CLK Trace 4: C/BEB0# Trace
2 This view shows the two word write of the latter part of the scope picture above. The STE reads the TX Buffer again and then does a write to TX DES0.Trace 1: FRAME# Trace 2: TRDY# Trace 3: PCI CLK Trace 4: C/BEB# Trace

 

Schematic of the DUT Card

Schematic of the DUT card

DUT card

Click here for high-definition PDF. Once PDF loads, use zoom tool to enlarge. We have built in extremely high resolution to show the critical silk-screen signal test points.

Ethernet Loopback

STE Block Diagram

Theoretical PHY Block Diagram in 100Base-TX mode

Figure 13. Theoretical PHY Block Diagram in 100Base-TX mode

STE10/100A datasheet pages

STE 10/100 Block Diagram

Figure 14. STE 10/100 Block Diagram

Industry Standard PCI Ethernet Tulip Software Driver